1. Field of the Invention
The present invention relates generally to logic circuit synthesis and more particularly relates to a computer-based method for size independent timing optimization of an initial logic design solution.
2. Description of the Related Art
Logic circuit synthesis involves a process of generating an initial circuit topology which satisfies the basic logic requirements and then optimizing the initial circuit topology to satisfy timing, load and physical area constraints. The initial design can be presented graphically as a schematic and also in a data file listing the included logic elements and their interconnection. The data file is generally referred to as a net list.
Optimization techniques operate on the net list to attain a satisfactory balance of the various circuit constraints. More specifically, timing correction is a technology dependent optimization of the net list where the goal is to meet the cycle time of the design. This is a phase of logic synthesis which involves extensive electrical and some boolean optimizations. The most important electrical optimizations are sizing and fan-out correction.
Timing correction in synthesis has traditionally operated on discrete libraries where there are discrete sized gates available for each gate type. A static timing analysis-based timing correction has typically been used, where various alternatives for sizes of the given type are attempted and a resulting error is evaluated. The error is generally referred to as "slack", which is a measure of the deviation from the simulated delay time compared to the desired cycle time. For example, an attempt to resize a particular gate in a design may involve trying out each alternative as a replacement in the design and reevaluating the slack for each trial. In a circuit whose critical path consists of N gates where each gate has M possible sizes, the cost of evaluating all possible alternatives is measured as M.sup.n .times.T, where T is the time required to evaluate each design alternative. As the size of the library (M) increases, the amount of processing power which is required for such an optimization quickly becomes significant.
In addition to the problem of processing overhead which is associated with the iterative approach typically employed in the prior art, the actual results from such a technique often deviate significantly from the simulation results. This is because traditional timing correction methods optimize the design based on an assumed wire load model. Typically, the wire loads seen by the output of a gate are assumed to be a function of the number of fan-outs of the gate. The size of each gate is selected during optimization based on this assumed wire load model. However, the assumed wire load model is often inaccurate, since no actual information regarding actual cell placement is available at this point in the optimization process.
Accordingly, there remains a need for a timing optimization approach which overcomes the shortcomings of prior art optimization solutions. The present invention employs a size independent approach which significantly reduces the iterative trial and error process used in previous methods and allows the size of gates to be selected after net list optimization, i.e., when gate placement information is available. This allows accurate modeling of the wire load presented at each stage of the circuit and accurate assignment of the associated gain for each stage.